Recently in the field of radio frequency (RF) communications, there has been an increased demand for digitally encrypted voice and high speed data communications. Since the RF spectrum is inherently limited, one must devise a new system concept and organizational features to accommodate the increased demand. A time division multiple access (TDMA) system is one such system which offers more efficient spectrum utilization and increased capacity.
In its simplest form, a TDMA system is comprised of a transmitting base station capable of time multiplexing messages from at least two users on a single RF channel, and one or more remote receiving stations capable of receiving at least one of the time multiplexed messages. Typically, the receiving station would be a mobile or portable radiotelephone capable of transmitting a TDMA message to the base station on a second RF channel.
In a TDMA system, like most digital communications systems, it is necessary to establish a reference clock in the receiving station that is continuously synchronized with the transmit clock in order to accurately recover the digital data transmitted between the two points. Continuous bit synchronization, as used herein, means that the frequency and phase of the received clock signal must accurately track that of the transmit clock.
Bit synchronization over a mobile communications channel can be difficult to maintain, primarily due to multipath fading. In addition to tracking the drift between the mobile and base station clocks, the clock recovery mechanism must be sufficiently tolerant of noise such that it does not readily lose synchronization during the periods of degraded signal-to-noise ratio caused by fading. Hence, an ideal TDMA mobile clock recovery circuit would have fast initial acquisition of symbol synchronization and continuously maintain synchronization with the base site clock, even during periods of severe signal fading.
One clock recovery technique which has been developed includes an early/late phase adjustment circuit with dual loop bandwidths. For acquisition of the clock from the received data signal, the system utilizes a control loop with a predetermined acquisition bandwidth. The acquisition bandwidth is wide, allowing for fast acquisition of symbol timing from the received data signal. However, the wide acquisition bandwidth results in significant steady-state timing jitter. Therefore, a tighter tracking bandwidth is used for improved steady-state performance. This dual bandwidth approach is relatively complex to implement, requiring acquisition-state and steady-state indicators, as well as a switchable loop bandwidth. In addition to increased implementation complexity, a conventional early/late approach with dual bandwidths has several performance problems associated with it. First, initial acquisition can be delayed considerably due to a false lock indication caused by random noise or interference. Second, if synchronization is lost due to a fade or signal dropout, reacquisition can be quite slow if the circuit does not detect the loss of lock. Finally, having only early and late phase adjustments inherently limits the speed of initial acquisition even if there are no other problems.
Therefore, a need exists for a clock recovery apparatus with a simple implementation and fast acquisition of symbol timing.